A fast prototype for modeling IP cores using in SoC with UML Marte.

Benabdallah Ahcene Youcef, Boudour Rachid

Abstract


The gap between production systems and technological development has been growing in recent times, leading to the reuse of predesigned and preverified components called Intellectual Property (IP). The growth of the latter is not going to happen without encountering some difficulties; we include among some a lack of standards for the implementation of IPs, making integration difficult, only one incentive to some types of hardware or software IPs and generally an incomplete development approach.            In this paper, we present a comprehensive approach for modeling an IPs starting from a metamodeling. The approach is based in a Model-Driven Engineering (MDA) methodology, used standards for SoC (Systems-on-Chip) specification, MARTE and Hardware Description Languages (HDLs).                       We illustrate our methodology in the case of USB 3.1, using Papyrus for modeling. Results are encouraging and show that the proposed approach allows creating cores of any size

Full Text:

PDF

References


N. Belhadj, Z. Marrakchi, M A. Ben-Ayed, N. Masmoudi, and H. Mehrez (2014). MPSoC Architecture for Macro Blocks Line Partitioning of H.264/AVC Encoder. International Journal of Embedded and Real-Time Communication Systems, 5(2), 43-60, PA: IGI Global publishing. doi: 10.4018/ijertcs.2014040104.

R. Damaševičius, and V. Štuikys (2005). Soft IP Customization Models Based on High-Level Abstractions. Information Technology and Control, 34(2), 125-134.

http://www.vsi.org

H. Posadas, J. Merino and E. Villar (2020). Data flow analysis from UML/MARTE models based on binary traces. Conference on Design of Circuits and Integrated Systems (DCIS), pp. 1-6, doi: 10.1109/DCIS51330.2020.9268671.

G. Ochoa-Ruiz, O. Labbani, E. Bourennane, Cherif, S. Meftali, and J. Dekeyser (2012). Enabling Partially Reconfiguration IP Cores Parametrisation and integration Marte and IP-XACT .23rd IEEE International Symposium on Rapid System Prototyping (RSP), (pp.107-113),Finland. PA :IEEE Publishing.

M. Keating and P. Bricaud (2002). Reuse Methodology manual for System-on-chip designs, Kluwer Academic Publishers. 3th editions, (pp. 312).

VSI Alliance. (1997). Architecture Document – Version 1.0. Technical report.

OMG. (2011). UML Profile for MARTE: Modeling and Analysis of Real-Time Embedded Systems. Version 1.1, 11-06-02, June 2011 http://www.omg.org/spec/MARTE/1.1

Universal Serial Bus 3.1 Specification July 26, 2013.https://manuais.iessanclemente.net/images/b/bc/USB_3_1_r1.0.pdf

N. Srivastava, A. C. Scogna and H. Shim (2018). Enabling the next generation USB 3.1 (Gen 2) in mobile devices. IEEE International Symposium on Electromagnetic Compatibility and 2018 IEEE Asia-Pacific Symposium on Electromagnetic Compatibility (EMC/APEMC), pp. 18-23, doi: 10.1109/ISEMC.2018.8393730.

R. Damasevicius and V. Stuikys (2004). Application of UML for hardware design based on design process model. ASP-DAC 2004 : Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753), pp. 244-249, doi: 10.1109/ASPDAC.2004.1337574.

S. Zhenxin and W. Weng-Fai (2009).A UML-based approach for heterogeneous IP integration. ASP-DAC09.

E. Piel , R B. Atitallah, P. Marquet , S. Meftali, S.Niar, A. Etien, J. Dekeyser and P. Boulet (2008). Gaspard2: from MARTE to SystemC Simulation, Proceedings of the DATE'08 workshop on Modeling and Analyzis of RealTime and Embedded Systems with the MARTE UML profile DATE’08, USA, 26-31.

A. Koudri, D. Vojtsiek, P. Soulard, C. Moy, J.Champeau, J. Vidal and J C. Le lann (2008). Using MARTE in the mopcom soc/sopc methodology. In workshop MARTE, Germany.

I.R. Quadri, A. Gamatié, P. Boulet, S. Meftali, J.L. Dekeyser (2012). Expressing embedded systems configurations at high abstraction levels with UML MARTE profile: advantages, limitations and alternatives. Journal of System and Architecture. 58 .

J. Vidal, F. De Lamotte, G. Gogniat, J P. Diguet and P. Soulard, P. (2009). IP reuse in an MDA MPSoPC co-design approach. International Conference on Microelectronics (ICM). (pp.256-259). PA: IEEE Publishing.

J. Vidal, F. De Lamotte, G. Gogniat, P. Soulard, J.P. Diguet. (2009). A Co-design approach for Embedded System Modeling and code generation with UML and MARTE. In Proceedings of Design Automation and Test in Europe, (DATE’09), (pp. 226– 231). Dresden, PA: IEEE Publishing.

N. Shimizu, M. Ikura, W. Wiriya, and S. Chivapreecha (2009). A new logic circuit design methodology with UML. In Proceedings of ITC-CSCC’09. (pp.62-65).

H. Posadas, P. Peñil, A. Nicolás, and E. Villar (2013).Automatic synthesis of embedded SW for evaluating physical implementation alternatives from UML/MARTE models supporting memory space separation. Microelectronics Journal. ISSN 0026-2692, 10.1016/j.mejo.2013.11.003

G. Ochoa-Ruiz, O. Labbani, E. Bourennane, P. Soulard, and S. Cherif (2012). A high-level methodology for automatically generating dynamic partially reconfigurable systems using IP-XACT and the UML MARTE profile. Journal of Design Automation for Embedded Systems, 16(3), 93-128, PA: Springer Publishing. DOI 10.1007/s10617-012-9098-6.

IEEE Standard for IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tools Flows," IEEE Std 1685-2014, vol., no., pp.C1-510, June. 12 2014.

A. Rautakoura, M. Käyrä, T. D. Hämäläinen, W. Ecker, E. Pekkarinen and M. Teuho, "Kamel: IP-XACT compatible intermediate meta-model for IP generation," 2020 23rd Euromicro Conference on Digital System Design (DSD), 2020, pp. 325-331, doi: 10.1109/DSD51259.2020.00060.

D D. Gajski and R. Kuhn (1983). Introduction: New VLSI Tools. Guest Editors', IEEE Computer, 16(12), 11-14.

H. Posadas, P. Peñil, A. Nicolás and E. Villar (2015). Automatic synthesis of communication and concurrency for exploring component-based system implementations considering UML channel semantics. Journal of Systems Architecture. Volume 61, Issue 8, 2015, Pages 341-360, ISSN 1383-7621,https://doi.org/10.1016/j.sysarc.2015.07.002.

http://www.cadence.com

http://www.eclipse.org/papyrus




DOI: https://doi.org/10.31449/inf.v45i6.3675

Creative Commons License
This work is licensed under a Creative Commons Attribution 3.0 License.